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Faculty Directory Dr. Anirban Ganguly
Dr. Anirban Ganguly

Dr. Anirban Ganguly

Associate Professor

[email protected]
Vidwan Profile Google Scholar

Academic Information

Ph.D, IIEST Shibpur, 2024

Research Areas

Neuromorphic Computing In-Memory Computing VLSI Deep Learning

Research Interests

1. Mixed-Signal Circuits & Systems: Designing hybrid analog-digital architectures. 2. VLSI Design: Specializing in current-mode architectures, DFT/FFT processors, and DCT realizations. 3. Neuromorphic Computing & AI Hardware: Developing resource-efficient VLSI for Deep Learning, activation functions (Softmax), and Artificial Neural Networks. 4. Signal Processing: Focusing on QAM-OFDM receivers and compressed sensing.

Courses Taught

Computer Networks
Computer Organization and Architecture
Signals and Systems
Digital Electronics

Positions Held

1. Associate Professor & Convener, IIC UEM Kolkata
2. Assistant Professor
3. Project Associate-II
4. Lecturer

Publications

  1. A. Ganguly, D. D. Mitra, and K. Garai, "A Mixed-Signal VLSI Architecture Design for ANN Based on MOS-Conductance Memory," Arabian Journal for Science and Engineering (SCIE), 2025 (will be included in the next issue of the Journal). 
  2. A. Ganguly, D. Datta, Mitra, M. Bhanja, A. Chakraborty, and A. Banerjee, "A Switched Current Mirror based VLSI Architecture of 1-D DCT for Compressed ECG Signal Acquisition," in Proc. 2024 IEEE Calcutta Conference (CALCON), 2025, pp. 1–5. 
  3. A. Ther, B. K. Pandit, A. Ganguly, A. Chakraborty, and A. Banerjee, "Resource-efficient VLSI Architecture of Softmax Activation Function for Real-time Inference in Deep Learning Applications," in Proc. 2023 International Symposium on Devices, Circuits and Systems (ISDCS), 2023, pp. 1–6. 
  4. R. D. Dey, B. K. Pandit, A. Ganguly, A. Chakraborty, and A. Banerjee, "Deep Neural Network Based Multi-Object Detection for Real-time Aerial Surveillance," in Proc. IEEE ESDC, 2023. 
  5. M. Bhanja, A. Ganguly, and S. R. Parija, "Graph Based Systematic Synthesis Procedure of gm-C Filter," in Proc. 7th International Conference on Electronics, Communication and Aerospace Technology, 2023. 
  6. A. Ganguly and A. Banerjee, "A Novel Reconfigurable Analog VLSI Architecture of M-point DFT Using Complex Matrix Multiplier and Graph-Based Signal Routing Method," Circuits, Systems, and Signal Processing (SCIE), vol. 41, pp. 5201–5225, 2022. 
  7. D. Kumar, A. Ganguly, P. Chakraborty, A. Chakraborty, B. Pandit, and A. Banerjee, "Low Power and High Precision Analog VLSI Design of 1-D DCT for Real-time Application," in Proc. 10th IEEE Region 10 Symposium (TENSYMP), 2022, pp. 1–5. 
  8. A. Ganguly and A. Banerjee, "Precise realization of one-staged 2-D DCT using analog current mode architecture in compressed sensing front-end," Microelectronics Journal (SCIE), vol. 115, pp. 1–9, 2021. 
  9. A. Ganguly and A. Banerjee, "VLSI architecture for analog radix-4 DFT front-end in QAM–OFDM receiver," Analog Integrated Circuits and Signal Processing (SCI), vol. 102, no. 1, pp. 169–179, 2020. 
  10. A. Ganguly, A. Chakraborty, and A. Banerjee, "A novel VLSI design of radix-4 DFT in current mode," International Journal of Electronics (SCI), vol. 106, no. 12, pp. 1845–1863, 2019.