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Binit Kumar Pandit

Binit Kumar Pandit

Assistant Professor

[email protected]
Vidwan Profile Google Scholar

Academic Information

  • Ph.D Submitted, IIEST Shibpur, 2026
  • M. Tech in VLSI Design, IIEST Shibpur, 2018
  • B.Tech in ECE, MDU Rohtak, 2016

Research Areas

AI/ML CNN VLSI Architecture Design Hardware Accelerators Image Segmentation

Research Interests

My research interests include computer hardware and VLSI architecture design for efficient AI/ML systems, with emphasis on resource-efficient and approximate computing techniques. I work on hardware acceleration of deep neural networks, including activation functions, pooling, FFT/DCT, and medical image processing applications. My interests also cover error-tolerant architectures, low-power and high-performance design, real-time inference, and hardware security aspects such as Trojan vulnerability analysis. Applications span medical imaging, aerial surveillance, and embedded intelligent systems.

Courses Taught

Computer Networks, Computer Organization & Architecture

Positions Held

Assistant Professor

Publications

Peer Reviewed Journals:

  1. B. K. Pandit, A. Chakraborty and A. Banerjee, “Error-Tolerant Medical Image Segmentation Using Resource-Efficient Approximate Booth Multipliers,” in IEEE Embedded Systems Letters, doi: https://doi.org/10.1109/LES.2025.36 12357.
  2. B. K. Pandit and A. Banerjee, “3d edgesegnet: a deep neural network framework for simultaneous edge detection and segmentation of medical images,” Signal, Image and Video Processing, vol. 17, no. 6, pp. 2981–2989, 2023, doi: https://doi.org/10.1007/s11760-023-02518-x.

International Conferences:

  1. B. K. Pandit and A. Banerjee, “VLSI Architecture of Sigmoid Activation Function for Rapid Prototyping of Machine Learning Applications,” 2021 IEEE International Symposium on Smart Electronic Systems (iSES), Jaipur, India, 2021, pp. 117-122, doi: https://doi.org/10.1109/iSES52644.2021.00036.
  2. A. Ther, B. K. Pandit and A. Banerjee, “VLSI Architecture of Generalized Pooling for Hardware Acceleration of Convolutional Neural Networks,” 2023 11th International Symposium on Electronic Systems Devices and Computing (ESDC), Sri City, India, 2023, pp. 1-5, doi: https://doi.org/10.1109/ESDC56251.2023.10149878
  3. A. Ther, B. K. Pandit, A. Ganguly, A. Chakraborty and A. Banerjee, “Resource-efficient VLSI Architecture of Softmax Activation Function for Real-time Inference in Deep Learning Applications,” 2023 International Symposium on Devices, Circuits and Systems (ISDCS), Higashihiroshima, Japan, 2023, pp. 01-05, doi: https://doi.org/10.1109/ISDCS58735.2023.10153520.
  4. M. Chaudhury, B. K. Pandit and A. Banerjee, “A Dynamic Window Size-Based VLSI Architecture Design of Moving Average Filter and Its Vulnerability to Hardware Trojans,” 2024 28th International Symposium on VLSI Design and Test (VDAT), Vellore, India, 2024, pp. 1-6, doi: https://doi.org/10.1109/VDAT63601.2024.10705727
  5. R. Dey, B. K. Pandit, A. Ganguly, A. Chakraborty and A. Banerjee, “Deep Neural Network Based Multi-Object Detection for Real-time Aerial Surveillance,” 2023 11th International Symposium on Electronic Systems Devices and Computing (ESDC), Sri City, India, 2023, pp. 1-6, doi: https://doi.org/10.1109/ESDC56251.2023.10149866.
  6. S. Chowdhury, B. K. Pandit and A. Banerjee, “Computation-Efficient and Multiplierless Hardware Realization of Decimation in Time FFT,” 2022 IEEE Region 10 Symposium (TENSYMP), Mumbai, India, 2022, pp. 1-6, doi: https://doi.org/10.1109/TENSYMP54529.2022.9864458.
  7. D. Kumar, A. Ganguly, P. Chakraborty, A. Chakraborty, B. K. Pandit, and A. Banerjee, “Low Power and High Precision Analog VLSI Design of 1-D DCT for Real-time Application,” in 10th IEEE Region 10 Symposium (TENSYMP), 2022, doi: https://doi.org/10.1109/TENSYMP54529.2022.9864386